The present invention relates generally to the field of memory and in particular to a system and method for synchronizing bank addresses between a controller and memory in a directed auto-refresh mode.
Microprocessors, digital signal processors, and other controllers perform computational tasks in a wide variety of applications, including embedded applications such as portable electronic devices. The trend is to ever-expanding feature sets and enhanced functionality of such devices, including increased memory, as well as more computationally powerful processors, in each product generation. Another trend of portable electronic devices is an ever-shrinking form factor. A major impact of this trend is the decreasing size of batteries used to power the controller, memory, and other electronics in the device, making power efficiency an increasingly important design goal. Hence, improvements to the controller and/or memory that increase execution speed and reduce power consumption are desirable, particularly for portable electronic device processors.
Dynamic Random Access Memory (DRAM) is well known in the art as being among the most cost-effective of solid state, or electronic, data storage technologies. DRAM stores binary data by charging or discharging individually addressable capacitive circuits. To achieve high bit density, and therefore low cost per bit, circuits that retain this charge indefinitely are omitted in DRAM technologies. Consequently, the charge dissipates due to leakage currents. To preserve the state of data stored in DRAM, the capacitive circuits storing bit values must be periodically charged, or “refreshed.”
DRAM arrays are commonly implemented as horizontal, rectangular, two-dimensional arrays comprising a plurality of rows and columns. Data bits are accessed by providing a row address and a Row Address Strobe (RAS) control signal, followed by a column address and a Column Address Strobe (CAS). Once a once a given row is accessed or “opened,” a large number of bit positions may be accessed by incrementing the column address. Thus, the delay in providing a row address and RAS signal may be amortized over many column accesses, particularly for long, sequential data accesses. This feature is further exploited by Fast Page Mode (FPM) and Extended Data Out (EDO) DRAM technologies, as known in the art. As higher densities of DRAM are packaged into modules, another organizational technique is to divide segments of memory into separately addressable banks. In a representative implementation, the memory address may be mapped to DRAM as shown below:
MSBLSBROWB1B0COLUMNBYTESELECT
The lower order bits may comprise a byte-select field, where the memory module provides data spanning several bytes in a single access. The next most significant bits are the column address, allowing data within the same row to be rapidly accessed. Above the row address are bank select bits, which independently address one of a plurality of DRAM banks (in this example, four banks). The row address comprises the more significant bits. Those of skill in the art will recognize that memory addresses may be mapped to the memory in a variety of ways; the above mapping is thus illustrative only, and not limiting.
Traditional DRAM is explicitly refreshed under the direction of a controller. The controller places the address of a row to be refreshed on the address bus, and asserts the RAS signal to refresh every memory storage location in that row. During a refresh cycle, all memory access operations are halted (i.e., no read or write operation may occur during a refresh cycle). A refresh counter in the controller provides the refresh row address, and the counter is incremented following each refresh cycle. All rows in the DRAM array may be refreshed sequentially. This is known in the art as a burst refresh, and must be executed once within the total required refresh time of the memory array. Alternatively, the controller may implement a distributed refresh, wherein refresh cycles directed to successive rows are interspersed among memory access cycles. The average allowable delay between distributed refresh cycles is the memory array total required refresh time divided by the number of rows.
With the advent of CAS-before-RAS refresh (CBR refresh), the controller was alleviated of the need to calculate and supply a row address for refresh cycles. A memory module that supports CBR refresh includes an internal row counter, which it increments upon receiving every CBR refresh cycle. The controller is unaware of which row is being refreshed at any given time; the controller is simply required to issue CBR refresh cycles within the required time period. The CBR refresh is one example of what is broadly referred to herein as auto-refresh—wherein a controller directs memory to issue a refresh cycle, but it is unaware of the specific row address being refreshed. In modern Synchronous DRAM (SDRAM) implementations, an auto-refresh cycle is commonly performed in response to the RAS and CAS signals being asserted simultaneously.
One disadvantage of conventional auto-refresh techniques (and additionally, traditional refreshes in which the controller supplies the refresh row address, if the banks are not independently refreshed) is that the controller is forced to close all DRAM rows to memory access operations (i.e. read and write accesses) prior to issuing an auto-refresh command. This may adversely impact processor performance by delaying data accesses and/or instruction fetches.
One solution, where the banks are independently refreshed, is for the controller to explicitly handle the refresh process by providing the row address and bank select information for each refresh command. In this case, the controller may direct a refresh cycle to one DRAM bank while simultaneously performing data access operations to remaining banks. A sophisticated controller may organize its memory operations to take advantage of this ability, thus improving performance.
A disadvantage of this approach, however, is that the controller cannot take advantage of the self-refresh mode offered by many modern memory implementations, which have particular applicability to portable electronic devices. In self-refresh mode, data is retained in the DRAM array during periods of inactivity, with minimum power consumption, and data access is disallowed. That is, data may not be written to or read from the DRAM array during self-refresh mode. DRAM with a self-refresh mode enables many circuits, including the controller, to enter an inactive or “sleep” mode to preserve battery power.
During self-refresh, the memory module cycles through the DRAM array, performing the minimum refresh activity necessary to maintain the data. To accomplish this, the memory module maintains an internal row/bank address counter that is not accessible to the controller. Upon exiting the self-refresh mode, the controller is not aware of which row was last refreshed in self-refresh mode, and consequently cannot continue explicit refresh operations unless it first performs a burst refresh to every row in sequence.